Normally, in digital baseband processing used in wireless transmission and reception, received signal power (received signal strength) is computed so as to perform control to measure a received signal status and to adjust parameters of a reception circuit according to a result thereof, or to feedback a value to a transmission side, so as to adjust transmission power to an optimum. In particular, in digital baseband processing in an OFDM (Orthogonal Frequency Division Multiplexing) system, a received signal is converted into subcarrier signals by FFT (Fast Fourier Transform) computation processing, and demodulation processing is performed on the subcarrier signal.
There are two methods of computing the power of a received signal:
(a) performing power computation for a received signal before FFT computation processing, and
(b) performing power computation for a subcarrier signal after FFT computation processing.
In (b), by designating a subcarrier signal whose power is to be computed, it is possible to compute the received signal power for a specific frequency range. Thus, for example, it is possible to use a method of computing the received signal power for a frequency exclusively allotted to a specific application, or of computing a frequency characteristic by performing a power comparison for each subcarrier.
For example, in Patent Document 1 (JP Patent Kokai Publication No. JP-A-09-8765), there is disclosed a configuration for computing the power of each of subcarrier signals obtained by performing computation processing, so as to compute a center frequency, and in this way performing frequency correction.
In Patent Document 2 (JP Patent Kokai Publication No. JP-P2002-261727A), there is disclosed a configuration for comparing the power of specific subcarrier out of subcarrier signals obtained by performing FFT computation processing, and selecting a reception antenna, in accordance with a result of the comparison.
These power computations, as shown in FIG. 10, are performed using an arithmetic circuit (power computation circuit) dedicated to power computation, or a processor such as a DSP (Digital Signal Processor), or the like. The power computation circuit or the DSP 702 compute the power from output of an FFT computation unit 701 to be outputted as received signal power.
It is to be noted that, as a butterfly computation in FFT computation, Patent Document 3, for example, discloses a configuration in which a radix 4 third stage can substantially execute with only code conversion and addition processing without multiplication processing, so that the configuration is that of an adder with a small size circuit, and third stage computation is performed in parallel with second stage computation. Furthermore, with regard to an accumulator provided with an adder and a register, reference is made, for example, to Patent Document 4. In addition, for detection of subcarriers in a multicarrier communication system, Patent Document 5 discloses a configuration in which time-direction correlation values of received data signals and replicas of an SCH (Synchronization Channel) symbol sequence are computed for all subcarriers, and subcarriers to which an SCH is assigned are detected based on the computed correlation values.